Digital measurement apparatus with improved expanded display

ABSTRACT

Digital measurement apparatus including means for receiving an input signal, means for storing a plurality of digital data representative of the input signal, and means for displaying the stored data for visual inspection. Means are provided for selecting any one of the displayed data points and for providing an expanded or multiplied display in which the selected point is at the center of the display and the number of adjacent data display points are determined by the selected point and the magnification factor. Means are also provided for varying the selected point during the expanded display, and for providing a rate of change of selected points proportional to the magnification factor of the expanded display.

United States Patent [191 [111 3,359,556 Schumann l l Jan. 7, 1975 DIGITAL MEASUREMENT APPARATUS WITH IMPROVED EXPANDED DISPLAY Inventor: Robert W. Schumann, Madison,

Wis.

Assignee: Nicolet Instrument Corporation,

Madison, Wis.

Filed: Nov. 15, 1972 Appl. No.: 306,907

US. 01. 315/24, 315/22, 178/75 SE, 235/92 N Int. Cl. H0lj 29/70 Field of Search 315/18, 19, 22, 24, 23; 235/92 N; l78/7.5 SE

References Cited UNITED STATES PATENTS Primary ExaminerMaynard R. Wilbur Assistant Examiner.l. M. Potenza Attorney, Agent, or Firm-Wayne A. Sivertson; Lew Schwartz [57] ABSTRACT Digital measurement apparatus including means for receiving an input signal, means for storing a plurality of digital data representative of the input signal, and means for displaying the stored data for visual inspection. Means are provided for selecting any one of the displayed data points and for providing an expanded or multiplied display in which the selected point is at the center of the display and the number of adjacent data display points are determined by the selected point and the magnification factor. Means are also provided for varying the selected point during the expanded display, and for providing a rate of change of selected points proportional to the magnification factor of the expanded display.

25 Claims, 16 Drawing Figures MEMOP 42- g W r COMP/IE- 4702 7 /4 9 cow [2752 1 P2? A l COMPUT- m 4 no PATENTEB JAN 71975 SHEET 10F a PATENTEU JAN 7 I975 SHEET 2 OF 4 DIGITAL MEASUREMENT APPARATUS WITH IMPROVED EXPANDED DISPLAY BACKGROUND OF THE INVENTION Digital measurement instruments are well-known in the art. Such instruments, for example signal averagers, pulse height analyzers, digital Oscilloscopes, and others, often use information display devices such as cathoderay tubes for graphic representations of the magnitudes of the measured variable as a function of an independent variable. For example, the graphic representation may comprise a set of several thousand coordinate points showing the manner in which an input voltage signal varied during a measurement period in which the voltage was measured at several thousand times following the start of the measurement period. The measured values are recorded in a storage device such as a digital memory, and the recorded data is repeatedly read from memory through appropriate circuitry to produce a rectangular coordinate display on the cathode-ray tube.

A disadvantage of such prior art digital measurement instrument has been that the displayed devices do not have sufficient resolution to show thousands of coordinate points meaningfully and even should such devices be capable of sufficient resolution, the circuitry used for providing the display from the storage device introduces sufficient noise and inaccuracies to cause difficulties in accurate reading of the display. Further, the displays are read with the human eye which cannot resolve certain details presented on a display screen of a typical cathode-ray tube without optical aids.

It is therefore apparent that there is a need to electrically expand the display scale, particularly in the horizontal access, in a manner such that only a restricted number of coordinate points are displayed at one time, with the operator having control over which coordinate points are to be displayed.

A commonly used method of achieving expansion is to electrically amplify voltages used to control the horizontal deflection of the beam of the cathode-ray tube. In this method, a bias voltage controlled by the operator is added to the deflection voltage to enable him to cause a particular portion of the data to appear on the screen, the other portions of the data being off screen because of the effect of the voltage amplification.

This method of voltage amplification is practical if only a few hundred coordinate points are of interest. However, if several thousand data points are involved this voltage amplification method is impractical because of the effects of the noiseand inaccuracies introduced in the process of decoding digital values for horizontal positioning control. For example, if 4096 coordinates are involved, a 12 bit digital-to-analog converter is required, but this converter must be accurate to far better than one part in 4096 if it is desired to show individual coordinates on the screen as discrete points rather than fuzzy line segments. Bias voltages and amplifier circuits must also be exceedingly stable and accurate. At present, the most complex and expensive horizontal deflection control circuits are scarcely capable of handling adequate expansion of scale by use of voltage amplification for 4096 point instruments and are entirely incapable of handling the problem for larger numbers of coordinate points, for example 16,000 or more points.

To solve this problem, another prior art method employs a technique of reading from memory only a portion of the information at a time. The memories of such systems are read out address sequentially, with the address number being used for control of horizontal positioning and the corresponding data value for a particular address number being used to control vertical positioning. The digital-to-analog converter for horizontal positioning may be one of 12 bits for a 4096 point system, and to provide for scale magnification the lower 10 bits, for example, of the address number may be applied to the upper 10 bits of the digital-to-analog converter. The upper 2 bits of the address number are ignored, but usually the memory read-out processes are controlled so that only one-fourth of the memory is addressed, for example an operators choice of addresses could be 0-1023, 1024-2047, 2048-3071, 3072-4095. For any one of these sets of addresses, the discarded upper 2 bits are the same throughout the set so there are no ambiguities. A four-fold scale expansion has taken place without adding errors since the expansion has been achieved digitally and exactly.

This prior art method of horizontal scale expansion, despite its advantages, also has at least two problems. First, because of the limitation to particular sets of data it often happens that only a portion of the particular data of interest to the operator can be seen on the expanded scale at one time. This makes it difficult for the operator who must keep switching from one expanded scale set of data to the other to interpret the point of interest. Second, the circuits and controls available to the operator for selection of which of the blocks of information will be displayed become increasingly complicated for expansion factors greater than four, though expansions as great as 64 are desirable in instruments with 4096 or more coordinate points involved. This problem generally results in limited and inadequate expansion factors.

The apparatus of this invention overcomes the abovementioned problems by providing for scale expansion by selectable factors which may be as large as desired, and by providing an unlimited choice of which consecutive coordinate points will be displayed with the selected expansion or magnification factor. Further, the apparatus of this invention provides for simple and rapid switching between an expanded or nonexpanded display, with a marker to indicate on the nonexpanded display the location of the coordinates which will be centered when the operator switches to an expanded display.

SUMMARY OF THE INVENTION Briefly described, the apparatus of this invention provides circuitry whereby the operator may operate a single control member to move a marker point along the coordinates of a nonexpanded display to select a point of interest. After selecting the point of interest the operator then selects a magnification factor and by means of a single switch causes an expanded display to appear. In the expanded display, the marked coordinate will automatically be at the center of the screen, and the adjacent coordinate points will begin and end with points stored in address numbers automatically selected by a factor dependent on the marked point and the magnification factor. Thus, the operator has an unlimited number of expansion sets or blocks of coordinate points. During an expanded display, the operator continues to have the option to move the marker to any of the coordinate points desired. As the marker is moved the newly selected coordinate point becomes the center of the display and the beginning and ending coordinate points also change, such that the display appears to move left or right across the face of the display scale, depending on which direction the marker is moved. The rate of change of the marker from one coordinate point to another is made to be inversely proportional to the magnification factor of the expanded display to avoid the problem whereby the display would change so quickly at high magnification factors that the operator would not have accurate control.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1(a)-1(2) are representations of displays of prior art digital measurement apparatus;

FIGS. 2(a)-2(c) are representations of the display of the digital measurement apparatus of this invention;

FIGS. 3(a)-3(c) are further representations of the display of the digital measurement apparatus of this invention;

FIG. 4 is a block diagram of the apparatus of this invention;

FIG. 5 is a block diagram of the position counter portion of the apparatus of this invention;

FIG. 6 is a block diagram of the read-out address counter portion of the apparatus of this invention;

FIG. 7 is a block diagram of the portion ofthe circuitry of the apparatus of this invention for determining the addresses to be displayed in the expanded display mode of the apparatus of this invention; and

FIG. 8 is a portion of the circuitry of the apparatus of this invention used to determine the position of displayed coordinate points on an expanded scale in the apparatus of this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT In FIGS. 1, 2 and 3 line drawings have been used to represent the displays to facilitate explanation. It will be recognized that in fact each of the displays represented in FIGS. 1-3 are made up of a plurality of points.

Referring first to FIGS. 1(a)-1(e), there are shown a plurality of display representations of the prior art device described above wherein the operator has a choice of a predetermined number of blocks or sets of addresses. FIG. 1(a) illustrates the appearance ofa representative display in unmagnified form. FIGS. l(b)-l(e) show the appearance of the display with four-fold magnification while displaying the four blocks of data. FIGS. 1(b) and 1(0) show normal blocks of addresses in an expanded scale. In FIGS. 1(d) and 1(e) the above mentioned problem with regard to a portion of interesting data not being fully available to the operator is'illustrated. In FIG. 1(d) a portion of the interesting feature is cut off at the right, and in FIG. 1(2) a portion of the data is cut off at the left. Therefore, in order to review the area ofinterest, the operator is limited to his predetermined sets or blocks of addresses and must continually switch from FIG. 1(d) to FIG. l(e) and back again to review the area of interest.

Throughout the remainder of this specification it will be assumed that the display device of the digital measurement apparatus of this invention is a cathode-ray tube, and that the horizontal deflection is produced by use of a digital-to-analog converter which receives the address (abscissa) values in digital form. It is apparent that other disply devices, such as a panel of lightemitting elements in matrix form could be used. The methods described herein can readily be applied to the control of column selection of such a device. The preferred displayed device, at the time of this writing, is the cathode-ray tube as it is readily available and comparatively inexpensive.

The displays produced by the apparatus of this invention are depicted in FIGS. 2 and 3. FIG. 2(a) shows a typical display in unexpanded form, and shows one coordinate labeled A, as brightened. This coordinate has been selected by the operator, in a manner to be described, and in the preferred embodiment identifies the centerpoint of the region which will be shown when the expanded display is used.

FIGS. 2(b) and 2(0) illustrate the appearance of the expanded display for the case of four-fold and eightfold expansion, respectively. The selected coordinate, A remains at horizontal screen center regardless of increases in expansion factors. Adjacent or neighboring coordinates appear to expand to the left and right with the screen center as the point about which expansion takes place. FIG. 3(a) shows the same wave form unexpanded, with the selection of A, moved tothe right. FIGS. 3(b) and 3(a) show the appearance of the expanded displays for this case, with four-fold and eightfold expansions, respectively.

In the preferred embodiment of the apparatus of this invention the operator may alter the selection of A, left or right as it would appear on the unexpanded display, during use of either an expanded or non-expanded mode. The position of A may be moved left or right one coordinate at a time at various rates of stepping. When altering the choice of A, during use of an expanded display, the brightened point remains at horizontal screen center, but the displayed wave form depicted by the display appears to move right or left across the screen. The rate at which the wave form moves left or right during an expanded display is controlled in a-manner such that the rate of change of the address of the selected point is proportionally slower for larger magnifications. For a given magnification, the rate of movement of a particular feature across the screen while changing the choice of position of A,- is therefore substantially constant. Without this rate of change adjustment, it would be difficult to center a particular feature on the screen while using large magnifications, as the features would move across the screen swiftly.

Another feature of the preferred embodiment of the apparatus of this invention, not shown in FIGS. 2 and 3 for purposes of clarity, is that at essentially all times the voltage value and time value of the coordinates of the selected point are displayed in numerical form so that the operator can obtain exact information about any coordinate by simply selecting it as A Such a numeric display is known in the prior art, see for example US. Pat. No. 3,662,373. However, in the apparatus of this invention a novel design for the numeric display includes the use of the same selection circuitry and controls for selecting the coordinate for numerical display as are used in selecting the region which will be displayed in analog form, expanded horizontally.

To best understand the apparatus of this invention, as explained in the specification in combination with the drawings, it will be helpful to first broadly discuss the portions of the circuitry and functioning of the improved novel expansion and selection apparatus. The preferred embodiment of the drawings includes measurement circuitry and a digital memory into which memory results are systematically recorded. The measurement circuitry is intended to be merely illustrative, and in the preferred embodiment is shown as being suitable for measuring a time-varying voltage. Other measurements, for example pulse height analysis, can be handled by circuits readily devised by those skilled in the art to which the apparatus of this invention may be applied. The digital memory of the preferred embodiment is assumed to be 4096 words of 12 bits per word. In the apparatus of this embodiment, the measured voltage values are recorded in memory sequentially, the first into address 0, the last into address 4095.

In the preferred embodiment, the selection and expansion functions may be generally described as follows. The unexpanded display will show one point marked or brightened to identify the center of the region which will be displayed when an expanded display is in use. The indication of the extent of the selected region is implicit from the setting of a magnification selector switch.

Several arithmetic functions are required of the display control circuits during use of the magnified display:

1. From the address number of the selected point and from the magnification desired, the address number of the first coordinate to be displayed must be computed. For example, in this embodiment 4096 coordinate points are involved. If the selected coordinate has an address number A and the magnification factor, M, is four, then usually the first displayed point will be 512 addresses lower than A,. In most cases, defining A, as the address of the first point to be displayed,

A0 A, 4096/2M 2. There are exceptions to 1., above. If A, 4096/2M is less than zero, the first address to be involved is address zero, since there are no negatively numbered memory addresses. This situation is illustrated in FIG. 2b. There must be circuits which recognize that A 4096/2M is negative and which cause A0 in such cases to be zero.

3. Generally, the first displayed point is at the left edge of the viewing screen, as in FIGS. 2c, 3b, and 3c. The exception is where A, 4096/2M is negative. In such cases the first point displayed, that corresponding to A0 O'as in FIG. 2b, is displayed at a position x=2048-MA,, presuming that position x==0 is at the left edge of the viewing screen and F4095 is at the right edge. Circuits responsive to the recognition circuits which sense that A, 4096/2M is negative cause the first displayed point to be at x=2048-MA, in such cases, otherwise to be at x=0.

4. Circuits are required which cause successive points to be spaced M units apart horizontally in consecutive order, following the display of the first point.

5. Circuits are required to recognize when the last coordinate of the selected set of coordinates has been displayed. Sometimes this could be on the basis of the number of points which have been displayed, usually 4096/M being the number of points within the set, since the screen can accommodate essentially only that many. However, in cases such as illustrated in FIG. 2b

or 3b, fewer points will be involved. This basis is therefore required which sense, on another basis than a count of the number of points already displayed, when the last point has been displayed. .A convenient basis is that if the coordinate whose address number is 4095 is being displayed, or if the coordinate being displayed is at the screen position x=4096-M, then the last point of the selected set has been reached.

The preferred embodiment includes means for computation and recognition as outlined above. It includes digital-to-analog converter circuits to convert the display position digital information to suitable deflection voltages for controlling both the horizontal and vertical positioning of the cathode-ray tube. Also included are means for altering upwards or downwards the selection of a particular coordinate point as the center point of the set of points to be shown when an expanded view has been selected. By center point is meant that point which will be shown at position F2048, the center of the viewing screen.

Referring now to FIG. 4, the block diagram of the abovedescribed system is shown. An analog-to-digital converter 1, a clock 3, an address counter 6 and an address selector 5 operate in a manner which at appropriate times causes digital information relating to the amplitude of the input signal voltages to be entered in memory. In the preferred embodiment, no display process takes place during the measurement, the address selector allowing only the measurement addresses to operate upon the memory. During display operations, selector 5 selects only display addresses.

It will be apparent that under some circumstances it may be preferable to intersperse measurement and dis play processes, and that this can be done without departing from the principles of the present invention. As mentioned above, the measurement circuits shown herein are intended to be merely illustrative.

A clock 15, a readout address counter 14, a subtraction circuits22, an updown counter 23 and a display position counter 11 are involved in determining and providing to other circuits the digital values representing the position and memory addresses of the first or leftmost point to be displayed, and the values of the positions and addresses of the coordinates to be displayed, as well as in determining how many coordinates will be displayed.

The state of updown counter 23 is equivalent to the address number of the selected center coordinate point. The state of counter 23 can be altered upwards or downwards by a control switch '79. A magnifier selector switch 41 is used by the operator to select the magnification or expansion factor. In the preferred embodiments the operator can select a magnification factor, M, of 1, 2, 4, 8, 16 or 32.

A pair of digital-to-analog converters 8 and 9 receive digital information pertaining to ordinate values and horizontal positions, respectively, from memory 2 and display position counter 11, for controlling the beam of cathode-ray tube 10 accordingly.

A comparator 7 senses equivalence between the address currently being utilized by memory 2 during display operations and the state of updown counter 23. When equivalence is sensed, comparator 7 provides an output voltage to display unit 10 which causes a brightening of the corresponding displayed coordinate for identification or marking purposes. Comparator 7 also provides this voltage signal to a buffer 64, and that signa] allows the corresponding digital ordinate value to be entered into buffer register 64. Display unit 70 displays in numerical form the ordinate value of the coordiriate having the selected addres number. Display unit 72 continually displays in numerical form the value of the address corresponding to the selected coordinate.

Clock 15 provides, through a divider 25, a continuous series of pulses to a switch 79. The pulses at switch 79 have a frequency inversely proportional to the amount of magnification selected on switch 41. At this To best understand the operation of the apparatus of this invention as shown in FIG. 4 it should be understood that thisinvention differs from prior art digital measurement and display devices particularly in .the manner in which the memory is addressed during display operations and in the manner in which the horizontal display position is controlled. The memory addressing involves a requirement that a succession of address numbers be generated in incremental sequence beginning with a certain number called A, and ending with some higher address number whose magnitude depends upon what display scale magnification is in use as upon what portion of the measured voltage waveform is being displayed. The display horizontal position control generates a succession of position numbers beginning with a certain number called X and ending with some higher position number the magnitude of which also depends upon the magnification in use and upon which portion of the waveform is being displayed.

Memory 2 may be assumed to have 4096 address 10- cations into which have been recorded 4096 measured voltage values here called ordinates. The display viewing screen, in this embodiment, is a cathode-ray screen. It may be considered as having a width of 4096 units. Distances in a horizontal direction may be considered as being measured from the left border of the viewing area. The distance to the right from this border to a particular position is defined as the distance x. As will be seen, the response of the beam deflection circuitry to the application of a particular horizontal position number of magnitude x is to cause the beam to be positioned x units to the right of the left border.

It is required that two related but usually different sets of numbers be generated, one to control memory addressing and one to control beam positioning. The numbers in these sets may be identified as A,- and X, for the jth numbers in the address control and position control number sets, respectively. The jth number in each set is made available to memory address and beam positioning circuits, essentially simultaneously. Those particular numbers are made available for some time, 10 microseconds for example being adequate, before the next pair of numbers is provided to the addressing and beam positioning circuits.

The number sets may be concisely defined. The set of address numbers is:

-9 lli-l) 0 1 2 3 w k-l Where x has a certain value to be defined, not necessarily equal to A and X X M The number A is equal to the quantity A,4096/2M unless than quantity is negative, in which case A O. The number x has the value 2048 MA if (A 4096/2M) is negative, otherwise x 0.

Each of the two sets contains k numbers. k is a positive integer equal to the smallest integer such that A 40% and x 4096.

' Given a particular magnification factor M. and a particular selected coordinate address number A both sets of numbers can easily be determined. The cases illustrated in FIGS. 2b and 3b are representative, and the sets of numbers for these two cases will be discussed.

The situation shown in FIG. 2b is comparable to the case in which the address number, A,,, of the selected coordinate is 490 and M 4.

(A 4096/2M) 22, therefore A 0 and x 2048 MA 88 The constant k has been determined simply by continuing the sets until one of them has reached the largest number less than 4096; there will be k numbers in each set, necessarily, and in this case k 1002.

The situation depicted in FIG. 3b is comparable to the case in which A, 3843 and M 4.

(A,4096/2M) 3331, so A, 3331, and x 0 A,, 4095; (kl) is evidently 764, as there are 764 terms from 3331 to 4095 and x 0 X1: 4 X2: 8

None of the computations involved in generating these sets of numbers is difficult, particularly in the preferred embodiment wherein M is always an integral power of two which makes it easy to form the quotient 4096/2M. Once the initial numbers of the set, A, and x have been computed it is easy to compute the remaining numbers in the sets by use of binary counters, for successive members of one set differ by an integer.

Also, it is easy to recognize .when'the lkth member in e if ther set has been reached-by use'of carry circuits used within thesecounters.

In this embodiment, i tisdesi rableftorepeatedly supply the two 'sets ofnumbers-tothe'address andfdeflection circuitry, and obviously desirable to supply the jth number in each set essentiallysimultaneously. This isachieved'in the manner to bedesc'ribed.

FIG. is adiagram of a portionof the position hum-" ber set generationcircuitry. Storage register 100is a 12 bit flip-flop register which response to each clock pulse applied by way of conductor lfifassumes one of two states,.either that corresponding to, the 12 bit humber output of adder l02jt ransmitted by way of 12 conductorcable 1 or an initialpositionnumberx, ap-

plied from external circuits to be described, by way of 12 conductor cable 28. If the voltage'f rorn or". "gate 101 applied by way of conductor'18is positiv'e;the regthe set has been reached, so the next clock pulse on conductor 13 causes the register 100 to assume the state equivalent to the initial position x,,.

Thus, the output of register 100 corresponds to the desired series x x,,-l'M, x,,+2M, x,,+(kl)M, x,,,

, FIG.I6 shows the address number set generator. Register 1l2 is identical in design to register 100 of FIG.

5 Thelsum formed by increment adder 113 is alwaysway of 12 conductor cable 27flf the position carry ister'assumes sta'te x otherwise it 'assurnesthefstatecorrespondingtothe,adder output."Register 100 is of common and well-known design. lt may be c omprised, I for example, ofl'three integrated circuits o f theftype known ,as the type'1749f8TTL four-bit latch manu fac tured by Texas- Instruments, -lnc. wired as reeoin- Q mended by thei manufacturertooperate'as a l2'bitjreg isterhSuchregis ters respondto an fedge? ofthje clock pulse, accepting information 'existingat the inputterminals at thatflinstant. his true that'the outputrapidly changes, which can quickly cause a change in the input number magnitude because of the action of the adder,

from adder 102 of FI-G. 5, or from adder 113, is positive, the register assumes state Agin response to the next clock pulse. This assures that wheneither A, or x,

is at the highest-possiblevalue (A,- -14095 or x,- 4096- but such i put number changes occur afterthe e dge f of the clock pulse has had its effect so, as is well known, the operation is unaffected by the changed input nuni- 1 her until the next clock pulse-occurs. Its state is trans mitted to external circuits to be described and to-adder 102 by way of 12 conductor cable 66. A'dde'r102 isaf conventional 12 bit binary adder which providesat es- 1; sentially all times the sum of the 12bit number from.

register 100 plusa constant equal to M, themagnifica tion factor,: applied by way of conductors 203-208 from gates 103-108. M has six possible values; 1, 2,4,; A 8, 16, or 32 represented by ground potentials on all y g be either A,-4096/2M if that quantity is positive, othwires 203 208 except one, which is positive. The value M=1 is represented'by all wires 203-208Qat gIQLlndpQ I I tential exceptwire 208; M=2 is the same except thatitr is wire 207 whichis positive. M*-4, 8,16, and 32 are the same except that wire206, 205,204, and 203, respectively, are positive..Gates 103-108 are conventional,

for example TTL type'logic gates. They receive, from an external source tobe described, a coded number,in., v the form of three bit binary numbersbyway of conduc tors 76, 77 and 78; the least significant bit being trans: mitted. on conductor -76, and the most significant onf conductor 78.- The conventional symbolism used in de;

picting gates 103%108 indicatesthe manner in which all conductorsY203-208 are held at ground potential except the appropriate conductor, The value, M,is trans mitted in this three bit jcode, rather than. in conventional binary number form, as a convenience for other M) both registerswill next assume their initial value (A, and x,,) in unison, when the next jclock pulseoccurs. 1 W M The position counter and address counter of FIGS, 5 and 6 therefore continually produce two related sets of numbers, transmitted to external circuits by way of 12- conductor cables 66 and 61, respectively. The numbe'rs, x x x x and A A A A,,- have initial values x and A, equal to the magnitudes of the initial position value and the initial address value presented by way of 12 conductor cables 28 and 27 respectively. The-position numbers have successively larger values, with the increase being equal to 2,", n being received on conductor 76, 77, and7 8l in binary represen- "tation. The address values haveincrementally increasing values. Both number sets contain k terms, the last term being that when either the address. number reaches the value 4095, or the positionlnumber reaches 0 the value 4096-2. Both number setsare generated re- -peatedly.

. As has been stated above, the initialaddress A,,, must erwise it must be zero. The initial display position x,,, must be zero if A, 4096/2M is negative, otherwise it must be 2048MA,;

g FIG, 7 shows the circuits which form this difference. Adder 202is a conventional 12 bit binary adder. Themagnitude of the number A,, the selected address numbe r,:is provided by way of 12 conductor cable 71 hav ing conductors 226--237 each representing the 12 bits l of A aA carry input is provided to the adder at terminal 5. Conductors 213-22 5 transmit a binary number to the-adder; it will be-seen that this number (combined with the carry input) is equivalent to 4096/2M.

For a particular value of M, the states of signals M Ill/I and M havea particular combination of ls and 0s.. For M=l, these are 000; for M=2, they are 001;

circuits to be described involving multiplication and division;

Or gate 101 provides a positive output on conduc 3 v tor 18 iftheadder 102 provides a positive carry signal output on conductor 109,-or if another carry signalto be described is positive, transmitted by conductor 80.

As will beseen, this carry ORd with the carry from adder 102, indicates that the kth position number of and so on, since M=2". The binary number is generated by a switchingcircuit to be described. For the combination .000, gate 203 produces an output signal 0 (ground potential) at conductor 213, andalll other conductors 214-225 are positive. The conductors 2l3-225 convey the binary number 0111 1111 1111 to the adder. .With the carry appliedto the adder, the output sum. is. A, 2048,"which is A', 4096/2M for the case where M=l. If the binary number n is 001, M is equal to 2,

v The term MA, is formed bya and it can be seen that the adder output will be A ,l024..IFor'any n, the adder output will be A,4096/2(2), as'required. If the addet produces a carry output, -409 6/2(2") is positive, otherwise 1 negative; Gates 203-210 combined with positive voltages on conductor's- -222 225 provide the complement of the number14096/2M, and the familiar method is used of adding the complement of one number to a second number in order to. generate another binary number equivalent to the difference. The difference'is used 'by external circuits only if that difference is positive, so 7 no consideration needbe given to the adderoutput number un'less a carry is present. s

. The adder output, a 12bit number, is transmitted to gate circuits'306 by way of 12 conductor'cable 307. yGate circuits a (A, -4096/2M) on 12 conductor cable 27 if the carry out signal transmitted by conductor 74'is positive. Oth- 3 .erwise the'output ofthe gate circuitsiscatised to be the binary number zeroQSuchgate circuits called'data se- 306 transmit the lectors are well-known. The output signal from gate circuits 306 'is therefore A g-4096/2M if that quantity is positive; otherwise that output iszero. This isthe desired value ofA and: A qistran'smitted to readout address counter 112 Of FIG. way of cable 27.

FIG. indicates the design of the circuits which provide the number x to thefdisplay position counter of FIG. 5.-The value x, is 2048-MA, if thecarryout signal from adder 202 of FIG. 7 is o, o therwi'se x1, is caused to be equal to zero.

which, since M can have onlyjthe values 1, 2, 4, 8, l6,

adder output v I data selector circuit 1 i or 32 in this embodiment, forms the productby a shift in bit positions,-the number of bit positions being equal 'to n; Only the least significant 12 bits of the product MA need'be used, since MA, never exceeds2048 in cases where ,1: is to be made equal to 2048-MA This is because if A,- 4096/2M is positive, x must becaused' to be equal 'to zero rather than equalto 2048-MA, Therefore, if the value of x, is to involve the use of MA MA, must be 2048 or less and therefore has 12 i or fewer significant bits. The design of multiplier'309 is easily devised by thosecskilled in the art;-

Subtraction circuits 310 receive the binary number} equal to MA by wayof 12' conductor cable'313, and

provide an output number equal top2O48-"M'A to gate" to the lowere dg'e of thescree n,

circuits 312 by way of cable 311. Gate circuits 31'2 pro-. 1

vide a 12 bit output signal representing the initial dis-. i

play position x to display position counter lljoffFlG.

4, by means of 12 cond'uctor cable 2 8; Gate circuits 312 receive a sign'zbit signal by. wa of, wire 74 from adder 202 of FIG. 7."Thatsign -bit',r-the carry signal'frbm adder 202, is positive ,if 'A,4'0,96/2M is positive; When that carry signal is positive," it is'desire'd thatx", bejmad'e equal to zero, otherwise x must be equal to-2048-MA Gate circuits 312 may easily be'designedtoproduce either zero or 2048-MA, at itsoutput. v

It has now been shown how the sets'of readout addresses numbers, A}, and display position numbers, x',-,'. are generated. Referring to FIG. 4, it can be seen that these address numbers are transmitted to address selector circuits 5, which are conventional data selector cir'.- v

cuits, which receive readout addresses by way of cable 61, measurement addresses from measurement address counter 6 to be described, and a control signal by way ground potential, otherwise it is at a positive voltage +V.;When that conductor is positive, the measurement address numbers appear at the output terminals of se- "lector 5, otherwise readout address numbers A,- appear.

The numbers which appear at the output terminals of selector 5 are transmitted by way of cable 52 to memory 2. For the present discussion of display operations, it will be assumed that the arm of switch 90 is in the downward position, so readout address numbers generated by readout address counter 14 are received by memory 2.

Memory 2 provides a 12 bit output number at cable 53 which at almost all times represents the number previously recorded at the address corresponding to the address number applied from selector 5 by way ofcable r 52.. The exception is a brief uncertain period which inevitably occurs during a change in address number, the

effect of which will be discussed below. The memory output numbers will be referred to as ordinate values, and later it will be shown how they are recorded in memory. Memory 2 circuits are well-known and widely used. In this embodiment, the memory has 4096'addresses and the ordinates are 12 bit numbers Digital-to-analog. converter 8 receives ordinate values by way of cable 53, and produces output voltages which are linearly related to thevalues received. These voltages are transmitted to cathode-ray tube display unit 10 by wayof wir'e 67.'Display-1 unit 10 -is awellknown device; it may forlexample byra Tek'tronix model 503'display oscilloscopeoperated ,in "what is 'known as the xy mode, wherein voltages applied to the vertical deflection input terminal cause the cathode-ray tu be beam to be deflectedvertically, an d vol ta'ges ap- 1 plied to the horizontal deflection input terminal'cause theb'eam to' be de'flected horizontally. The amount of -'deflections-arelinearly related tothe existing voltage values, and adjustments may be made so that a voltage,- equal to zero'appiiejd tothe-vertical deflection input 40 terminal causesine beamto bedeflected to the lower edge o'f the'view'ingfarea, and a voltage equal'to 4.095

. causesthe beam tobe deflec'tedtothe'top edge. lf digital-to-analog converter 8 is adjusted to .produce output voltages equal to one millivolt' per unit input number magnitude, the beam will be .deflectedvertically in proportion totheordinatevalues, with'zerocorresponding to be deflected to'the'le'ftiedgeot'. theviewing area and position number4095 causesdefl'ection to the-right edge;

, Clock 15 produces periodic pulses.atits and these are 'tra'nsmittedv to counters 11am; 14, causing the address numbers A, and position nuinber's'x, to be generated in sequence as describe'd 1.Tliebeam of dis-' play unit 10 isthereforecaused to produce a coordiofconductor 38 from mode switch 90. When the switch arm is in the downward position, conductor 38 is at nate display of the ordinate values versus address numbers, as desireduwhich address will be involved, and which; horizontal display scale will be used depend upon the presentstate of updown coun'ter 23-and the.

presently" seiected value of M, the'mag nification factor.

Magnifier switch 41, FIG. 4, may be set in anyone of sixpossible positions. The output voltages M M and y I M on conductors 76, 77, and 78 represent a three bit binary number whichcorresponds to the constant n,

and M has been defined as equal to 2". The binary number n is represented by voltages on conductors 76, 77, and 78; a ground potential representing-a 0, and a positive voltage representing a 1. The least significant bit appears at conductor 76; the most significant at conductor 78.

Switch 93 is a control switch which causes n to'become equal to zero regardless er the setting ofswitch 41, for all contacts become grounded if switch 93 is in the. off positiotnThe wiper contact of switch 93 is conr nected to theswitch 41 contacts 401, 403, 405,. 408,

417, 415mm 416-by means of wire94. 17- y Updown counter 23 is a conventional binary updown counter of well-known design. It receives pulses on conductors 30 or 31 from control switch .79, when that:

switch is actuated by the operatorso that the wiper arm makes contact with conductor 30 or-3l. In response to each pulse received on conductor 30*the stateof, counter 30 increases by one step; it decreases one jstepf' for each pulse received on conductor 31. Counter 23 1 receives a controlsignal from switch 93 by way of con- I ductor 94 which causes the output number from counter 23 to become equal to 2048 if the voltage on 5 that conductor is zero, otherwise the output of counter 23 corresponds to the state of that counter That state isythe number A the addr ess number of the selected. coordinate. This control of the output of counter 23 by v i the presenceof a ground or'a positive voltage on conductor 94 involves use of siinple data selection circuits within counter 23, readily devised byf-those'skilled' in the art. 1 w x When conductor 94 is at gro been shown that n.=.0, so M=l and the selected address number, A,,, is equal to 2048/The number sequences}.

x, and A,- then become identical and stepfro m O' L I- through 4097 in single steps, forithisis the response'of r the address and position number sequence generating circuits previously described'The display istherefore g g non-magnified and all coordinatesaredisplayed:

in the manner illustrated in FIGS. 2b, 2c, 3b an'd 3c.

Divider 25 receives the number corresponding to n, by way of conductors 76,77 and 78, and receivesa continuous train of pulses at a frequency of lOOKh from clock by way of conductorl 3 'xDivider is designed to provide output' pulses on conductor 32 connected tothe wiper arm 26 of switch 32.Theoutput pulse repetition rate varies inversely proportional to 2", 1 with a rate of 400 Hz for n=0, and 12.5 Hz for n=- 5. Di-

vider circuits are well-known, and circuits which provide the variable frequency output pulses according to the magnitude of n are easily devised by those skilled in the art.

The variable stepping rate insures that when utilizingf a high display magnification, the changesin A,, when operatingswitch 79, will not be so rapid as to cause the apparent movement of the displayed information across the screen to be so rapid asto make it impossible 'to cause a particular feature to be approximately posilf conductor 94 is at a positiveyoltageztheselected l T addressnumber, A corresponds to the statefo f updown counter 23, and .thecoordinatelwhose address number is equal to A, will be'displayed at screen cen-,

ter. Other coordinates will be displayed onthe screen conversion is completed.

tioned'onscreen. The maximum rate of change of 400 1 steps per second allows A to be changed from any value to any other value'in less than ten seconds, so this is a reasonable choice of frequency.

i -Numeric'display unit 72 receives the number A, by

means of cable 71, and produces a visible numerical indication of thevalue of the number. Such display devices are inlcommon use, and may contain binary to decimal conversion circuits ifdecimal displays are consideredpreferable to binary or actal displays. This numeric. display is nota necessary part of this invention but is a preferred convenience.

Numeric display'unit 70 is a similar device which receives ordinate information by way of cable 24 from.

buffer 64. Buffer 64 ise' 12bit register which receives ordinate information from memory 2 by way of cable 53.A control pulse is received by buffer 64 from com- .parator7 byiwey of conductor during the time the pulse is positive buffer 64 accepts; the 12 bit ordinate number and holds it thereafter until the next'pulse. The control pulse fro'm compar ator 60 exists at all, times in whichaddressnumber 'A received by way of cable 71 agrees with the presentreadout address A,- received by cable 61. The presence ofthe control pulse therefore i causes buffer 64 to accept and hold ordinate information corresponding to the memory address whose mumberis displayed by numericdisplayunit 72. Buffer 64 and numeric display unit are noftnecessary for the .foperation' of the cathode-ray tubedisplay rnagnifica v tion circuits, but is-a preferred convenience. l

The output voltageof comparator .7isl also transmittedtogthe beam:intensifierterminal of the display unit 10. "Fliesbearn current is increased thereby whenever lthewreadoutfaddress n u'mbenisthe, same as'A The l'br'ightenedpoint identifies'the coordinate whose. address numberfand ordinate value,areflnumerically dis played wheneiipansion on-off switch 93OfFIG. 4 is y w rngthe off (downwardlposition', the brightened displayed pointidentifi'es the center of the region which 'vvill beshown if that switch-isther rplaced 'in the up- :wa'rds positionl to. causev the'display horizontal scale to are manywaysin which data may be measured .The addressinto which this information iswritten is controlled 'by binary address counter 6, the output numbers olfgwhich are applied to'address selector S'by pi way. of cable .63.Modeswitch isjplacedin the upward position when it is desired to measure and record I a variable, so: the voltage or cond uctor38 is positive thereby making address selector 5 responsive to the output ofaddress counter 6 rather than the output of l address counter 14.

Clock 3 is of such design that it produces a series of pulses which are transmitted to analog-to-digital converter l. The pulse recurrence rate is arbitrary, for example l millisecond. That clock will not produce output pulses unless enabled by a positive voltage on conductor 28, and also not until a start pulse is received at terminal 40 from external devices. When the start pulse is received, the clock 3 output pulses occur, causing converter 1 to make measurements. After each measurement, the end-of-conversion is signalled by an output pulse on conductor 49, connected to address counter 6 and memory 2. Each such end-of-conversion pulse causes the measured value output of converter 1 to be recorded in the memory. At the end of each endof-conversion pulse, address counter 6 is advanced in state by one step.

A ground potential on conductor 38 causes the address counter to be cleared to state zero, so the first measured signal voltage value is recorded in memory address zero, the next in address one, and so on, until address 4095 is reached. The next end-of-conversion pulse received from converter 1 by the counter 6 causes a stop pulse output to occur, transmitted from counter 6 to clock 3 by way of conductor 47. This causes the clock 3 to discontinue the generation of output pulses until the next start pulse is received at terminal 40.

The design of clock 3 circuits, address counter 6 circuits, and analog-to-digital converter 1 circuits may have many variations. Such circuits are widely used in measuring devices known as digital signal averages. The characteristics of these circuits can easily be achieved by designs familiar to those skilled in the art.

From the abovedescription of the preferred embodiment of the apparatus of this invention it will be appar' ent that the improved selection and expansion circuitry provide significant advantages over prior art digital measurement apparatus. It will also be apparent that certain modifications to the circuitry and additions not shown in the preferred embodiment can be made without departing from the spirit and scope of this invention.

It is apparent, for example, that the use of up-down counter 23 for controlling the selection of the center point of the display is but one of several ways in which the selection can be made. Mechanical switches, or a control with a shaft angle encoder, could be used although the up-down counter is preferred.

it is also apparent that the selected point could be I marked by means other than by brightening the point.

Furthermore, the use of the center point, rather than some other point such as the leftmost point, is a matter of preference.

What is claimed is:

1. In digital measurement apparatus including input means for receiving a signal and providing a plurality of data points representative of the signal, storage means connected to the input means for storing the data points in storage addresses, and display means connected to the storage means for visual display of the data points, the improvement comprising: first means connected to the storage means and the display means, for selecting any desired data point; second means connected to the first means and the display means for providing thereto a selectable magnification factor; and the first means including further means responsive to the selected data point and the selected magnification factor for controlling the addresses and display positions of data points to be displayed on the display means.

2. The apparatus of claim 1 including: means connected to the first means and the second means for varying the rate of change from one selected data point to another by a factor inversely proportional to the selected magnification factor.

3. The apparatus of claim 1 including: numeric display means connected to the first means and the storage means for displaying in numerals the measured values of the selected data point.

4. The apparatus of claim 3 in which the numeric display means comprises: first and second numeric display devices; the first device connected to the storage means and the first means for displaying the value of the selected data point; and the second device connected to the first means for displaying the storage location of the selected data point.

5. The apparatus of claim 1 in which: the first and further means include means for providing that the selected data point is always at the horizontal center of the visual display on the display means.

6. The apparatus of claim I in which: the first means '7 includes means for brightening the selected data point on the display means.

7. The apparatus of claim 1 in which the further means includes: means-for determining a set of ad dresses of data points to be displayed, the set comprising:

A A A A A A and means for determining a set of position numbers for the data points to be displayed, the set comprising:

A,,=A,-Y/2M if positive, otherwise A,,=0

x,,=Y/2-MA if (A,Y/2M) is negative, otherwise A the address of the selected data point Y the total number of addresses in the storage means M the selected magnification factor k a positive integer equal to the smallest integer such that A Y and x Y.

8. In digital measurement apparatus having input means for receiving an electrical signal to be measured and including means for providing a plurality of data points representative of the signal, memory means having a plurality of storage addresses, the memory means connected to the input means for storing the data points in sequential addresses, and display means connected to the memory means for providing a visual coordinate display of data points, the improvement comprising: means including address counter means connected to the memory means for cyclically providing addressed data points to be displayed; data point selection means including storage means for storing a selected address; comparator means having input means connected to the address counter means and the storage means, and having output means connected to the display means for providing a signal for marking a selected data point; magnification selector means connected to the data point selection means for providing any one of a plurality of selectable magnification factors thereto; first control means connected to the data point selection means, the address counter means and the magnification selector means; the first control means including means responsive to the selected address and the selected magnification factor for controlling the addresses of the data points to be displayed; second control means connected to the first control means, the magnification selector means, the address counter means and the display means; the second control means including means responsive to the selected address and the selected magnification factor for controlling the abscissa position of data points to be displayed on the display means; and clock means connected to the address counter means, the data point selection means and the second control means, for providing clock pulses thereto.

9. The apparatus of claim 8 including: numeric display means; and means connecting the numeric display means to the memory means and the comparator means output means for providing a numeric display of the ordinate value of the selected data point.

10. The apparatus of claim 9 including: further numeric display means; and means connecting the further numeric display means to the data point selection means for providing a numeric display of the selected address number.

11. The apparatus of claim 8 in which the data point selection means storage means comprises an updown digital counter.

12. The apparatus of claim 11 including: up-count input means and down-count input means on the counter means; and manually operable switch means connected between the clock means and the up-count input means and down-count input means, for changing the state of the counter means, selectively.

13. The apparatus of claim 11 including: frequency controller means; means connecting the frequency controller means between the clock means and the switch means; and means connecting the divider means to the magnification selector means, for varing the rate of change of the state of the counter means.

14. The apparatus of claim 8 in which: the first and second control means include means for positioning the selected data point at the center of the visual coordinate display of data points on the display means.

15. The apparatus of claim 8 including: further manually operable switch means; means connecting the further switch means to the data point selection means and the magnification selector means for selectively inhibiting operation thereof when a nonmagnified display is desired.

16. The apparatus of claim 8 in which: the display means includes means responsive to the marking signal from the comparator means for brightening the selected data point on the visual coordinate display.

17. In display apparatus for cyclically displaying the contents of the addresses of a digital storage means as points on a visual coordinate display, the improvement comprising: first means for selecting any address; control means; expansion means for providing a selectably variable expansion of the abscissa distance between points in the visual coordinate display; means connecting the first means to the control means; means connecting the control means to the expansion means, the digital storage means and the display apparatus; and the control means including means for providing that the content of the selected address is displayed as a point at the abscissa center of the visual coordinate display.

18. The apparatus of claim 17 in which: the display apparatus includes means connected to the control means for visually marking the displayed point of the selected address. I

19. The apparatus of claim 17 in which the first means includes: counter means; and means for selectively changing the state of the counter means for se lecting any address.

20. The apparatus of claim 19 in which the means for selectively changing the state of the counter means includes: means connected to the expansion means for varying the rate of change of the state of the counter means by a factor inversely proportional to the selected expansion.

21. The apparatus of claim 17 including: further display means connected to the control means and the digital storage means for providing a visual numeric display of the contents of the selected address.

22. The apparatus of claim 17 including: further display means connected to the first means for providing a visual numeric display of the selected address.

23. The apparatus of claim 17 in which the control means includes: digital computation means responsive to the selected address from the first means and the selected expansion from the expansion means, for controlling the addresses to be displayed as points in the display apparatus visual coordinate display, and the position of the points on the visual coordinate display.

24. The apparatus of claim 23 in which the digital computation means includes: means for controlling the addresses to be displayed according to the formula:

A A A A A where;

A A Y/2M if positive, otherwise A =0 A, the selected address Y the total number of addresses in the storage means M the selected expansion k a positive integer equal to the smallest integer such that A Y.

25. The apparatus of claim 23 in which the digital computation means includes: means for controlling the position of displayed points according to the formula:

x x x x x where;

x Y/2 MA if (A, Y/2M) is negative, otherwise A; the selected address.

Y the total number of addresses in the storage means M the selected expansion k a positive integer equal to the smallest integer 

1. In digital measurement apparatus including input means for receiving a signal and providing a plurality of data points representative of the signal, storage means connected to the input means for storing the data points in storage addresses, and display means connected to the storage means for visual display of the data points, the improvement comprising: first means connected to the storage means and the display means, for selecting any desired data point; second means connected to the first means and the display means for providing thereto a selectable magnification factor; and the first means including further means responsive to the selected data point and the selected magnification factor for controlling the addresses and display positions of data points to be displayed on the display means.
 2. The apparatus of claim 1 including: means connected to the first means and the second means for varying the rate of change from one selected data point to another by a factor inversely proportional to the selected magnification factor.
 3. The apparatus of claim 1 including: numeric display means connected to the first means and the storage means for displaying in numerals the measured values of the selected data point.
 4. The apparatus of claim 3 in which the numeric display means comprises: first and second numeric display devices; the first device connected to the storage means and the first means for displaying the value of the selected data point; and the second device connected to the first means for displaying the storage location of the selected data point.
 5. The apparatus of claim 1 in which: the first and further means include means for providing that the selected data point is always at the horizontal center of the visual display on the display means.
 6. The apparatus of claim 1 in which: the first means includes means for brightening the selected data point on the display means.
 7. The apparatus of claim 1 in which the further means includes: means for determining a set of addresses of data points to be displayed, the set comprising: A0, A1, A2, A3, A4, . . ., A(k 1); and means for determining a set of position numbers for the data points to be displayed, the set comprising: x0, x1, x2, x3, x4, . . ., x(k 1); where Ao As-Y/2M if positive, otherwise Ao 0 Ai A(i 1)+1 xo Y/2-MAs if (As-Y/2M) is negative, otherwise xo 0 xi x(i 1)+M As the address of the selected data point Y the total number of addresses in the storage means M the selected magnification factor k a positive integer equal to the smallest integer such that A(k 1) < Y and x (k 1) < Y.
 8. In digital measurement apparatus having input means for receiving an electrical signal to be measured and including means for providing a plurality of data points representative of the signal, memory means having a plurality of storage addresses, the memory means connected to the input means for storing the data points in sequential addresses, and display means connected to the memory means for providing a visual coordinate display of data points, the improvement comprising: means including address counter means connected to the memory means for cyclically providing addressed data points to be displayed; data point selection means including storage means for storing a selected address; comparator means having input means connected to the address counter means and the storage means, and having output means connected to the display means for providing a signal for marking a selected data point; magnification selector means connected to the data point selection means for providing any one of a plurality of selectable magnification factors thereto; first control means connected to the data point selection means, the address counter means and the magnification selector means; the first control means including means responsive to the selected address and the selected magnification factor for controlling the addresses of the data points to be displayed; second control means connected to the first control means, the magnification selector means, the address counter means and the display means; the second control means including means responsive to the selected address and the selected magnification factor for controlling the abscissa position of data points to be displayed on the display means; and clock means connected to the address counter means, the data point selection means and the second control means, for providing clock pulses thereto.
 9. The apparatus of claim 8 including: numeric display means; and means connecting the numeric display means to the memory means and the comparator means output means for providing a numeric display of the ordinate value of the selected data point.
 10. The apparatus of claim 9 including: further numeric display means; and means connecting the further numeric display means to the data point selection means for providing a numeric display of the selected address number.
 11. The apparatus of claim 8 in which the data point selection means storage means comprises an updown digital counter.
 12. The apparatus of claim 11 including: up-count input means and down-count input means on the counter means; and manually operable switch means connected between the clock means and the up-count input means and down-count input means, for changing the state of the counter means, selectively.
 13. The apparatus of claim 11 including: frequency controller means; means connecting the frequency controller means between the clock means and the switch means; and means connecting the divider means to the magnification selector means, for varing the rate of change of the state of the counter means.
 14. The apparatus of claim 8 in which: the first and second control means include means for positioning the selected data point at the center of the visual coordinate display of data points on the display means.
 15. The apparatus of claim 8 including: further manually operable switch means; means connecting the further switch means to the data point selection means and the magnificAtion selector means for selectively inhibiting operation thereof when a nonmagnified display is desired.
 16. The apparatus of claim 8 in which: the display means includes means responsive to the marking signal from the comparator means for brightening the selected data point on the visual coordinate display.
 17. In display apparatus for cyclically displaying the contents of the addresses of a digital storage means as points on a visual coordinate display, the improvement comprising: first means for selecting any address; control means; expansion means for providing a selectably variable expansion of the abscissa distance between points in the visual coordinate display; means connecting the first means to the control means; means connecting the control means to the expansion means, the digital storage means and the display apparatus; and the control means including means for providing that the content of the selected address is displayed as a point at the abscissa center of the visual coordinate display.
 18. The apparatus of claim 17 in which: the display apparatus includes means connected to the control means for visually marking the displayed point of the selected address.
 19. The apparatus of claim 17 in which the first means includes: counter means; and means for selectively changing the state of the counter means for selecting any address.
 20. The apparatus of claim 19 in which the means for selectively changing the state of the counter means includes: means connected to the expansion means for varying the rate of change of the state of the counter means by a factor inversely proportional to the selected expansion.
 21. The apparatus of claim 17 including: further display means connected to the control means and the digital storage means for providing a visual numeric display of the contents of the selected address.
 22. The apparatus of claim 17 including: further display means connected to the first means for providing a visual numeric display of the selected address.
 23. The apparatus of claim 17 in which the control means includes: digital computation means responsive to the selected address from the first means and the selected expansion from the expansion means, for controlling the addresses to be displayed as points in the display apparatus visual coordinate display, and the position of the points on the visual coordinate display.
 24. The apparatus of claim 23 in which the digital computation means includes: means for controlling the addresses to be displayed according to the formula: A0, A1, A2, A3, . . ., A(k 1) where; A0 As - Y/2M if positive, otherwise A0 0 Ai A(i 1) + 1 As the selected address Y the total number of addresses in the storage means M the selected expansion k a positive integer equal to the smallest integer such that A(k 1) < Y.
 25. The apparatus of claim 23 in which the digital computation means includes: means for controlling the position of displayed points according to the formula: x0, x1, x2, x3, . . ., x(k 1) where; x0 Y/2 - MAs if (As - Y/2M) is negative, otherwise x0 0 xi x(i 1) + M As the selected address. Y the total number of addresses in the storage means M the selected expansion k a positive integer equal to the smallest integer such that A(k 1) < Y. 